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Freescale Semiconductor Data Sheet: Technical Data
Document Number: MC9S08MP16 Rev. 1, 10/2009
MC9S08MP16 Series Data Sheet
Features
* 8-Bit HCS08 Central Processor Unit (CPU) - Up to 51.34 MHz CPU at 2.7V to 5.5V across temperature range of -40C to 105C - Up to 40 MHz CPU at 2.7V to 5.5V across temperature range of -40C to 125C - HC08 instruction set with added BGND instruction and additional addressing modes for LDHX and STHX - Support for up to 48 interrupt/reset sources * On-Chip Memory - Up to 16 KB flash memory; read/program/erase over full operating voltage and temperature - Up to 1 KB random-access memory (RAM) - Security circuitry to prevent unauthorized access to RAM and flash memory contents * Power-Saving Modes - Two low power stop modes; reduced power wait mode - Peripheral clock gating can disable clocks to unused modules * Clock Source Options - Oscillator (XOSC) -- Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25-38.4 kHz or 1-16 MHz - Internal Clock Source (ICS) -- Containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolutions and 2% deviation over temperature and voltage; supports CPU frequencies up to 51.34 MHz * System Protection - Watchdog computer operating properly (COP) reset running from dedicated 1-kHz internal clock source or bus clock - Low-voltage detection with reset or interrupt; selectable trip points - Illegal opcode and illegal address detection with reset - Flash memory block protection * Development Support - Single-wire background debug interface - Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus three more breakpoints in on-chip debug module) - On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module supports both tag and force breakpoints * Peripherals - IPC -- Interrupt Priority Controller with 4 programmable interrupt priority levels - ADC -- 13-channel, 12-bit resolution; 2.5 s conversion time; automatic compare function; 1.7 mV/C temperature sensor; internal bandgap reference channel; operation in stop3
48-LQFP Case 932-03 28-SOIC Case 751F-05
32-LQFP Case 873A-03
- PGA -- Differential programmable gain amplifier with programmable gain (x1, x2, x4, x8, x16, or x32) - HSCMP -- Three fast analog comparators with positive and negative inputs; separately selectable interrupt on rising and falling comparator output; filtering; windowing; HSCMP1 and HSCMP2 outputs can be optionally routed to FTM1 module; runs in stop3 - DAC -- Three 5-bit digital to analog convertor used as a 32-tap voltage reference for each comparator - PDB -- Two programmable delay blocks: PDB1 synchronizes PWM with samples of ADC; PDB2 synchronizes PWM with comparing window of analog comparators - SCI -- Full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake up on active edge - SPI -- Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; Master or Slave mode; MSB-first or LSB-first shifting - IIC/SMBus -- Up to 400 kbps; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer; supports broadcast mode and 10-bit addressing; SMBus compatible - FTM -- Two Flextimers with total of 8 channels; One 2-channel (FTM1) and one 6-channel (FTM2); supports operation up to 2x bus clock; selectable input capture, output compare, edge- or center-aligned PWM; dead time insertion; fault inputs - MTIM -- 8-bit modulo counter with 8-bit prescaler - RTC -- (Real-time counter) 8-bit modulus counter with binary or decimal based prescaler; External clock source for precise time base, time-of-day, calendar or task scheduling; Free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components, runs in all MCU modes - CRC -- Cyclic redundancy check generator - KBI -- Three 8 channel keyboard interrupt module with software selectable polarity on edge or edge/level modes * Input/Output - 40 GPIOs, 2 output-only pins. - Hysteresis and configurable pull up device on input pins; Configurable slew rate and drive strength on output pins; Sink/Source current up to 20mA * Package Options - 48-LQFP, 32-LQFP, 28-SOIC - 48-LQFP qualified for automotive usage
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) Freescale Semiconductor, Inc., 2009. All rights reserved.
Table of Contents
1 2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .9 2.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .9 2.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .10 2.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .11 2.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .15 2.8 External Oscillator (XOSC) Characteristics . . . . . . . . .20 2.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .21 2.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.11 Digital to Analog (DAC) Characteristics . . . . . . . . . . . .26 2.12 High Speed Comparator (HSCMP) Characteristics . . .26 2.13 Programmable Gain Amplifier (PGA) Characteristics . 2.14 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.14.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 2.14.2 FTM Module Timing . . . . . . . . . . . . . . . . . . . . . 2.14.3 MTIM Module Timing . . . . . . . . . . . . . . . . . . . . 2.14.4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.15 Flash Memory Specifications. . . . . . . . . . . . . . . . . . . . 2.16 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.16.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Device Numbering Scheme. . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 27 27 28 29 30 33 33 33 34 35 35 35 35
3 4 5 6
MC9S08MP16 Series Data Sheet, Rev. 1 2 Freescale Semiconductor
Interrupt Priority Controller (IPC)
HCS08 CORE CPU BKGD INT BKP
ON-CHIP ICE DEBUG MODULE (DBG) CYCLIC REDUNDANCY CHECK (CRC) 8-BIT KEYBOARD INTERRUPT (KBI1) 8-BIT KEYBOARD INTERRUPT (KBI2) BKGD/MS 8-BIT KEYBOARD INTERRUPT (KBI3) IIC MODULE (IIC) KBI1P[7:0] PTA7/SPSCK PTA6/MOSI PTA5/SCL/MISO PTA4/TCLK/SDA/SS PTA3/SCL/FTM1CH1 PTA2/SDA/FTM1CH0 PTA1/SCL/RxD PTA0/SDA/TxD PTB7/KBI1P7/ADP7/C3IN4 PTB6/KBI1P6/CMP3OUT/ADP6/C3IN3 PTB5/KBI1P5/CMP2OUT/ADP5/C2IN4 PTB4/KBI1P4/ADP4/C2IN3 PTB3/KBI1P3/ADP3/C3IN2/PGAPTB2/KBI1P2/ADP2/C1IN2/PGA+ PTB1/KBI1P1/ADP1/C2IN2 PTB0/KBI1P0/ADP0/CIN1 PTC7/KBI2P7/TCLK PTC6/KBI2P6/FTM2FAULT PTC5/KBI2P5/FTM2CH5 PTC4/KBI2P4/FTM2CH4 PTC3/KBI2P3/FTM2CH3 PTC2/KBI2P2/FTM2CH2 PTC1/KBI2P1/FTM2CH1 PTC0/KBI2P0/FTM2CH0 PTD7/KBI3P7/CMP3OUT PTD6/KBI3P6/CMP2OUT PTD5/KBI3P5/CMP1OUT PTD4/KBI3P4/PDB2OUT PTD3/KBI3P3/FTM1FAULT PTD2/KBI3P2/PDB1OUT PTD1/KBI3P1/SCL PTD0/KBI3P0/SDA PTE6/EXTAL PTE5/XTAL PTE4/ADP12/C1IN4 PTE3/ADP11/C1IN3 PTE2/ADP10 PTE1/ADP9 PTE0/ADP8 PTF2 PTF1/RESET PTF0/BKGD/MS
HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP
KBI2P[7:0]
KBI3P[7:0]
RESET LVD USER FLASH
SCL SDA
(Only on MC9S08MP16)
2-CHANNEL FLEXTIMER (FTM1) 6-CHANNEL FLEXTIMER
(MC9S08MP16 = 16384 BYTES) (MC9S08MP12 = 12288 BYTES)
USER RAM
TCLK FTM1FAULT FTM2CH[5:0] TCLK FTM2FAULT TCLK
(FTM2) 8-BIT MODULO TIMER (MTIM) SERIAL COMMUNICATIONS INTERFACE (SCI) XTAL EXTAL SERIAL PERIPHERAL INTERFACE (SPI) PROGRAMMABLE DELAY BLOCK (PDB1) PROGRAMMABLE DELAY BLOCK (PDB2) 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) PROGRAMMABLE GAIN AMPLIFIER (PGA)
50.33 MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.4 kHz 1 MHz to 16 MHz (XOSC) REAL TIME COUNTER (RTC)
TxD RxD SS SPSCK MISO MOSI PDB1OUT PDB2OUT
VREFH VDDA/VREFH VSSA/VREFL
VOLTAGE REGULATOR
VREFL
VDD1 VSS1 VDD2 VSS2
PGA+ PGA- CIN1 C1IN2 C1IN3 C1IN4 CMP1OUT C2IN2 C2IN3 C2IN4 CMP2OUT C3IN2 C3IN3 C3IN4 CMP3OUT
(Only on MC9S08MP16)
DIGITAL-TO-ANALOG CONVERTER (DAC1)
HIGH SPEED ANALOG COMPARATOR (HSCMP1)
DIGITAL-TO-ANALOG CONVERTER (DAC2)
HIGH SPEED ANALOG COMPARATOR (HSCMP2)
DIGITAL-TO-ANALOG CONVERTER (DAC3)
HIGH SPEED ANALOG COMPARATOR (HSCMP3)
Notes: When PTF1 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pull-up device. When PTF0 is configured as BKGD, pin becomes bi-directional. VDD2 pad is tied internally on 32-pin and 28-pin packages, VSS2 pad is tied internally on 28-pin packages
Figure 1. MC9S08MP16 Series Block Diagram
MC9S08MP16 Series Data Sheet, Rev. 1 Freescale Semiconductor 3
PORT F
PORT E
ADP12-ADP0
PORT D
PORT C
(MC9S08MP16 = 1024 BYTES) (MC9S08MP12 = 512 BYTES)
PORT B
FTM1CH[1:0]
PORT A
pins not available on 28-pin packages pins not available on 32-pin or 28-pin packages
Pin Assignments
1
Pin Assignments
PTB6/KBI1P6/CMP3OUT/ADP6/C3IN3
38
This section shows the pin assignments for the MC9S08MP16 Series devices.
PTB5/KBI1P5/CMP2OUT/ADP5/C2IN4
37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24
48
47
46
45
44
43
42
41
40
PTC4/KBI2P4/FTM2CH4 PTC5/KBI2P5/FTM2CH5 PTC6/KBI2P6/FTM2FAULT PTC7/KBI2P7/TCLK PTD0/KBI3P0/SDA PTD1/KBI3P1/SCL PTD2/KBI3P2/PDB1OUT PTD3/KBI3P3/FTM1FAULT VSS1 VDD1 PTA0/SDA/TxD PTA1/SCL/RxD
1 2 3 4 5 6 7 8 9 10 11 12
39
PTB7/KBI1P7/ADP7/C3IN4
PTC3/KBI2P3/FTM2CH3
PTC2/KBI2P2/FTM2CH2
PTC1/KBI2P1/FTM2CH1
PTC0/KBI2P0/FTM2CH0
PTF0/BKGD/MS
PTE6/EXTAL
PTE5/XTAL
VDD2
VSS2
PTB4/KBI1P4/ADP4/C2IN3 PTE4/ADP12/C1IN4 PTE3/ADP11/C1IN3 VSSA/VREFL VDDA/VREFH PTB3/KBI1P3/ADP3/C3IN2/PGA- PTB2/KBI1P2/ADP2/C1IN2/PGA+ PTB1/KBI1P1/ADP1/C2IN2 PTB0/KBI1P0/ADP0/CIN1 PTE2/ADP10 PTE1/ADP9 PTE0/ADP8
PTF2
PTA2/SDA/FTM1CH0
PTA3/SCL/FTM1CH1
PTA6/MOSI
PTA4/TCLK/SDA/SS
PTD4/KBI3P4/PDB2OUT
PTD5/KBI3P5/CMP1OUT
PTD6/KBI3P6/CMP2OUT
PTD7/KBI3P7/CMP3OUT
PTA5/SCL/MISO
PTA7/SPSCK
PTF1/RESET
Note: Pins in bold are lost in the next lower pin count package.
Figure 2. MC9S08MP16 Series in 48-LQFP
MC9S08MP16 Series Data Sheet, Rev. 1 4 Freescale Semiconductor
Pin Assignments
PTB6/KBI1P6/CMP3OUT/ADP6/C3IN3 25 24 23 22 21 20 19 18 9 PTA1/SCL/RxD 10 PTA2/SDA/FTM1CH0 PTB5/KBI1P5/CMP2OUT/ADP5/C2IN4 PTB4/KBI1P4/ADP4/C2IN3 VSSA/VREFL VDDA/VREFH PTB3/KBI1P3/ADP3/C3IN2/PGA- PTB2/KBI1P2/ADP2/C1IN2/PGA+ PTB1/KBI1P1/ADP1/C2IN2 PTB0/KBI1P0/ADP0/CIN1 16 PTA7/SPSCK 17
PTC1/KBI2P1/FTM2CH1
PTC0/KBI2P0/FTM2CH0
PTF0/BKGD/MS
PTE6/EXTAL
32 PTC2/KBI2P2/FTM2CH2 PTC3/KBI2P3/FTM2CH3 PTC4/KBI2P4/FTM2CH4 PTC5/KBI2P5/FTM2CH5 PTC6/KBI2P6/FTM2FAULT VSS1 VDD1 PTA0/SDA/TxD 1 2 3 4 5 6 7 8
31
30
29
VSS2
28
PTE5/XTAL 27 14 PTA5/SCL/MISO
26
11
PTA3/SCL/FTM1CH1
12 PTF1/RESET
13 PTA4/TCL:K/SDA/SS
15 PTA6/MOSI
PTB7/KBI1P7/ADP7/C3IN4
Note: Pins in bold are lost in the next lower pin count package.
Figure 3. MC9S08MP16 Series in 32-Pin LQFP Package
MC9S08MP16 Series Data Sheet, Rev. 1 Freescale Semiconductor 5
Pin Assignments
PTC0/KBI2P0/FTM2CH0 PTC1/KBI2P1/FTM2CH1 PTC2/KBI2P2/FTM2CH2 PTC3/KBI2P3/FTM2CH3 PTC4/KBI2P4/FTM2CH4 PTC5/KBI2P5/FTM2CH5 PTC6/KBI2P6/FTM2FAULT VSS1 VDD1 PTA0/SDA/TxD PTA1/SCL/RxD PTA2/SDA/FTM1CH0 PTA3/SCL/FTM1CH1 PTF1/RESET
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PTF0/BKGD/MS PTB6/KBI1P6/CMP3OUT/ADP6/C3IN3 PTB5/KBI1P5/CMP2OUT/ADP5/C2IN4 PTB4/KBI1P4/ADP4/C2IN3 VSSA/VREFL VDDA/VREFH PTB3/KBI1P3/ADP3/C3IN2/PGA- PTB2/KBI1P2/ADP2/C1IN2/PGA+ PTB1/KBI1P1/ADP1/C2IN2 PTB0/KBI1P0/ADP0/CIN1 PTA7/SPSCK PTA6/MOSI PTA5/SCL/MISO PTA4/TCLK/SDA/SS
Figure 4. MC9S08MP16 Series in 28-Pin SOIC Package
MC9S08MP16 Series Data Sheet, Rev. 1 6 Freescale Semiconductor
Pin Assignments
Table 1. Pin Availability by Package Pin-Count
Pin Number 48
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
<-- Lowest 28
5 6 7
Priority Alt 2
FTM2CH4 FTM2CH5 FTM2FAULT TCLK1 SDA5 SCL5 PDB1OUT FTM1FAULT
--> Highest Alt3 Alt4
32 LQFP
3 4 5
Port Pin
PTC4 PTC5 PTC6 PTC7 PTD0 PTD1 PTD2 PTD3
Alt 1
KBI2P4 KBI2P5 KBI2P6 KBI2P7 KBI3P0 KBI3P1 KBI3P2 KBI3P3
-- -- -- -- --
6 7 8 9 10 11
-- -- -- -- --
8 9 10 11 12 13
VSS1 VDD1 PTA0 PTA1 PTA2 PTA3 PTD4 PTD5 PTD6 PTD7 PTF1 PTF2 PTA4 PTA5 PTA6 PTA7 PTE0 PTE1 PTE2 PTB0 PTB1 PTB2 PTB3 KBI1P0 KBI1P1 KBI1P2 KBI1P3 ADP8 ADP9 ADP10 ADP06 ADP16 ADP26 ADP36 CIN16 C2IN26 C1IN26 C3IN26 PGA+6 PGA-6 VDDA/VREFH VSSA/VREFL PTE3 ADP116 C1IN36 TCLK1 SDA5 SCL5 SS MISO MOSI SPSCK SDA5 SCL5 SDA5 SCL5 KBI3P4 KBI3P5 KBI3P6 KBI3P7 RESET4 TxD RxD FTM1CH0 FTM1CH1 PDB2OUT CMP1OUT CMP2OUT2 CMP3OUT3
-- -- -- --
12
-- -- -- --
14
--
13 14 15 16
--
15 16 17 18
-- -- --
17 18 19 20 21 22
-- -- --
19 20 21 22 23 24
--
--
MC9S08MP16 Series Data Sheet, Rev. 1 Freescale Semiconductor 7
Electrical Characteristics
Table 1. Pin Availability by Package Pin-Count (continued)
Pin Number 48
35 36 37 38 39 40 41 42 43 44 45 46 47 48
1 2 3 4
<-- Lowest 28 --
25 26 27
Priority Alt 2
ADP126
--> Highest Alt3
C1IN46 ADP46 C2IN36 C2IN46 C3IN36 C3IN46
32 LQFP --
23 24 25 26 27 28 29
Port Pin
PTE4 PTB4 PTB5 PTB6 PTB7 PTE5 PTE6
Alt 1
Alt4
KBI1P4 KBI1P5 KBI1P6 KBI1P7 XTAL EXTAL CMP2OUT2 CMP3OUT3
ADP56 ADP66 ADP76
-- -- -- -- --
28 1 2 3 4
VSS2 VDD2 PTF0 PTC0 PTC1 PTC2 PTC3 BKGD KBI2P0 KBI2P1 KBI2P2 KBI2P3 MS FTM2CH0 FTM2CH1 FTM2CH2 FTM2CH3
--
30 31 32 1 2
5 6
TCLK pin can be repositioned using TCLKPS in SOPT2. Default reset location is PTC7. HSCMP2 output CMP2OUT can be repositioned using the CMP2OPS in the SOPT2 register. Default reset location is PTD6. HSCMP3 output CMP3OUT can be repositioned using the CMP3OPS in the SOPT2 register. Default reset location is PTD7. Pin is open drain with an internal pullup that is always enabled. Pin does not contain a clamp diode to VDD and should not be driven above VDD. The voltage measured on the internally pulled up RESET will not be pulled to VDD. The internal gates connected to this pin are pulled to VDD. IIC pins SDA and SCL can be repositioned using IICPS in SOPT2. Default reset locations are PTD0 and PTD1. If ADC, HSCMP, or PGA is enabling a shared analog input pin, each has access to the pin.
2
2.1
Electrical Characteristics
Introduction
This section contains electrical and timing specifications for the MC9S08MP16 Series of microcontrollers available at the time of publication.
MC9S08MP16 Series Data Sheet, Rev. 1 8 Freescale Semiconductor
Electrical Characteristics
2.2
Parameter Classification
Table 2. Parameter Classifications
P C Those parameters that are guaranteed during production testing on each individual device. Those parameters that are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters that are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters that are derived mainly from simulations.
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
T D
NOTE
The classification is shown in the column labeled "C" in the parameter tables where appropriate.
2.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled. Table 3. Absolute Maximum Ratings
Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range
1
Symbol VDD IDD VIn ID Tstg
Value -0.3 to +5.8 120 -0.3 to VDD + 0.3 25 -55 to 150
Unit V mA V mA C
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins, except for PTF1/RESET are internally clamped to V SS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption).
MC9S08MP16 Series Data Sheet, Rev. 1 Freescale Semiconductor 9
Electrical Characteristics
2.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 4. Thermal Characteristics
Num 1 2 3 C -- D D Rating Operating temperature range (packaged) Maximum junction temperature Thermal resistance single-layer board
1,2
Symbol TA TJ
Consumer & Industrial -40 to 105 115
Automotive -40 to 125 135
Unit C C
48-pin LQFP 32-pin LQFP 28-pin SOIC 4 D Thermal resistance four-layer board
1,2
80 JA 85 71
80 -- -- C/W
48-pin LQFP 32-pin LQFP 28-pin SOIC
1
56 JA 57 48
56 -- -- C/W
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Junction-to-ambient natural convection
The average chip-junction temperature (TJ) in C can be obtained from: TJ = TA + (PD x JA) where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint + PI/O Pint = IDD x VDD, Watts -- chip internal power PI/O = Power dissipation on input and output pins -- user determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K / (TJ + 273C) Solving Equation 1 and Equation 2 for K gives: K = PD x (TA + 273C) + JA x (PD)2 Eqn. 3 Eqn. 2 Eqn. 1
MC9S08MP16 Series Data Sheet, Rev. 1 10 Freescale Semiconductor
Electrical Characteristics
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA.
2.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification, ESD stresses were performed for the human body model (HBM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless instructed otherwise in the device specification. Table 5. ESD and Latch-up Test Conditions
Model Human Body Description Series resistance Storage capacitance Number of pulses per pin Latch-up Minimum input voltage limit Maximum input voltage limit Symbol R1 C -- Value 1500 100 3 - 2.5 7.5 V V Unit pF
Table 6. ESD and Latch-Up Protection Characteristics
No. 1 2 3
1
Rating1 Human body model (HBM) Charge device model (CDM) Latch-up current at TA = 105C
Symbol VHBM VCDM ILAT
Min 2000 500 100
Max -- -- --
Unit V V mA
Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted.
2.6
DC Characteristics
Table 7. DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Num C 1 2 3 -- Operating Voltage
Characteristic
Symbol VDD
(2)
Condition
Min 2.7 -- --
Typ1 -- 0 0
Max 5.5 100 100
Unit V mV mV
-- Analog Supply voltage delta to VDD (VDD - VDDA) -- Analog Ground voltage delta to VSS (VSS -
VDDA VSSA
VSSA)(2)
MC9S08MP16 Series Data Sheet, Rev. 1 Freescale Semiconductor 11
Electrical Characteristics
Table 7. DC Characteristics (continued)
Num C C P C Output high 4 C voltage P C 5 D Output high current C P C 6 C P Output low C voltage 7 8 9 10 11 C P Input low voltage; all digital inputs 12 C 13 14 C Input hysteresis P Input leakage current (per pin) P 15 Hi-Z (off-state) leakage current (per pin) input/output port pins PTF1/RESET, PTE5/XTAL pins Pullup or Pulldown3 resistors; when enabled 16 P C D DC injection current
5, 6, 7, 8
Characteristic All I/O pins (except PTF1/RESET) low-drive strength
Symbol
Condition 5 V, ILoad = -4 mA 5 V, ILoad = -2 mA
Min VDD - 1.5 VDD - 0.8 VDD - 0.8
Typ1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max -- -- -- -- -- -- -100 1.5 0.8 0.8 1.5 0.8 0.8 1.5 0.8 0.8 100 -- -- 0.35 x VDD 0.35 x VDD
Unit
VOH
3 V, ILoad = -1 mA
V
5 V, ILoad = -20 mA VDD - 1.5 high-drive strength 5 V, ILoad = -10 mA VDD - 0.8 3 V, ILoad = -5 mA Max total IOH for all ports All I/O pins (except PTF1/RESET) low-drive strength All I/O pins (Except PTF1/RESET) high-drive strength PTF1/RESET VOL IOHT VOUT < VDD 5 V, ILoad = 4 mA 5 V, ILoad = 2 mA 3 V, ILoad = 1 mA 5 V, ILoad = 20 mA 5 V, ILoad = 10 mA 3 V, ILoad = 5 mA 5 V, ILoad = 3.2 mA 5 V, ILoad = 1.6 mA 3 V, ILoad = 0.8 mA Max total IOL for all ports IOLT VIH VOUT > VSS 5V 3V VIL 5V 3V Vhys VDD - 0.8 0 -- -- -- -- -- -- -- -- -- 0 0.65 x VDD 0.7 x VDD -- -- 0.06 x VDD VIn = VDD or VSS --
mA
V
C P C D Output low current
mA V
P Input high voltage; all digital inputs
V
V -- 1 A
|IIn|
|IOZ|
VIn = VDD or VSS VIn = VDD or VSS
-- --
-- --
1 2
A A
I/O pins RPU,RPD PTF1/RESET4 RPU
17 17
37 37
52 52
k k
Single pin limit 17 Total MCU limit, includes sum of all stressed pins IIC
VIN > VDD VIN < VSS VIN > VDD VIN < VSS
0 0 0 0
-- -- -- --
2 -0.2 25 -5
mA mA mA mA
MC9S08MP16 Series Data Sheet, Rev. 1 12 Freescale Semiconductor
Electrical Characteristics
Table 7. DC Characteristics (continued)
Num C 13 14 15 16 Characteristic Symbol CIn VRAM VPOR tPOR VLVD1 VDD falling VDD rising P Low-voltage detection threshold -- low range VDD falling VDD rising P Low-voltage warning threshold -- high range 1 VDD falling VDD rising P Low-voltage warning threshold -- high range 0 VDD falling VDD rising P Low-voltage warning threshold low range 1 VDD falling VDD rising P Low-voltage warning threshold -- low range 0 VDD falling VDD rising T Low-voltage inhibit reset/recover hysteresis 23 24 25
1 2 3 4 5
Condition
Min -- -- 0.9 10
Typ1 -- 0.6 1.4 --
Max 8 1.0 2.0 --
Unit pF V V s
C Input Capacitance, all pins C RAM retention voltage C POR re-arm voltage9
D POR re-arm time P Low-voltage detection threshold -- high range
17
3.9 4.0 VLVD0 2.48 2.54 VLVW3 4.5 4.6 VLVW2 4.2 4.3 VLVW1 2.84 2.90 VLVW0 2.66 2.72 Vhys 5V 3V -- -- 1.18 VBG 1.17
4.0 4.1
4.1 4.2
V
18
2.56 2.62
2.64 2.70
V
19
4.6 4.7
4.7 4.8
V
20
4.3 4.4
4.4 4.5
V
21
2.92 2.98
3.00 3.06
V
22
2.74 2.80 100 60 1.202 --
2.82 2.88 --
V
mV -- 1.21 1.22 V V
P Bandgap voltage reference at 25C10 P Bandgap voltage reference across temperature range10
6
Typical values are measured at 25C. Characterized, not tested DC potential difference. When keyboard interrupt is configured to detect rising edges, pulldown resistors are used in place of pullup resistors. The specified resistor value is the actual value internal to the device. The pullup value may measure higher when measured externally on the pin. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
MC9S08MP16 Series Data Sheet, Rev. 1 Freescale Semiconductor 13
Electrical Characteristics
7 8
All functional non-supply pins except PTF1/RESET are internally clamped to VSS and VDD. The PTF1/RESET pin does not have a clamp diode to VDD. Do not drive this pin above VDD. 9 Maximum is highest voltage that POR is guaranteed. 10 Factory trimmed at VDD = 5.0 V
2
125C 25C -40C
1.0 Max 1.5V@20mA 0.8 VOL (V) 0.6 0.4 0.2 0
125C 25C -40C
Max 0.8V@5mA
1.5 VOL (V)
1
0.5
0
0
5
10 15 IOL (mA) a) VDD = 5V, High Drive
20
25
0
2
4 6 IOL (mA) b) VDD = 3V, High Drive
8
10
Figure 5. Typical VOL vs IOL, High Drive Strength (except PTF1/RESET) 2
125C 25C -40C
1.0 Max 1.5V@4mA 0.8 VOL (V) 0.6 0.4 0.2 0
125C 25C -40C
Max 0.8V@1mA
1.5 VOL (V)
1
0.5
0
0
1
2 3 IOL (mA) a) VDD = 5V, Low Drive
4
5
0
0.4
0.8 1.2 IOL (mA) b) VDD = 3V, Low Drive
1.6
2.0
Figure 6. Typical VOL vs IOL, Low Drive Strength (except PTF1/RESET)
MC9S08MP16 Series Data Sheet, Rev. 1 14 Freescale Semiconductor
Electrical Characteristics
2
125C 25C -40C
1.0 Max 1.5V@ -20mA 0.8 VDD - VOH (V) 0.6 0.4 0.2 0
125C 25C -40C
Max 0.8V@ -5mA
1.5 VDD - VOH (V)
1
0.5
0
0
-5
-10 -15 -20 IOH (mA) a) VDD = 5V, High Drive
-25
0
-2
-4 -6 -8 IOH (mA) b) VDD = 3V, High Drive
-10
Figure 7. Typical VDD - VOH vs IOH, High Drive Strength 2
125C 25C -40C
1.0 Max 1.5V@ -4mA 0.8 VDD - VOH (V) 0.6 0.4 0.2 0
125C 25C -40C
Max 0.8V@ -1mA
1.5 VDD - VOH (V)
1
0.5
0
0
-1
-2 -3 IOH (mA) a) VDD = 5V, Low Drive
-4
-5
0
-0.4
-0.8 -1.2 -1.6 IOH (mA) b) VDD = 3V, Low Drive
-2.0
Figure 8. Typical VDD - VOH vs IOH, Low Drive Strength
2.7
Supply Current Characteristics
Table 8. Supply Current Characteristics
Num C C 1 C P 2 C Parameter Run supply current measured at (CPU clock = 4 MHz, fBus = 2 MHz) Run supply current3 measured at (CPU clock = 16 MHz, fBus = 8 MHz)
3
This section includes information about power supply current in various operating modes.
Symbol
VDD (V) 5
Typ1 2.16 1.8 5.26 4.92
Max2 3
Unit
RIDD
mA 3 5 2.5 7.5 mA 3 7
RIDD
MC9S08MP16 Series Data Sheet, Rev. 1 Freescale Semiconductor 15
Electrical Characteristics
Table 8. Supply Current Characteristics (continued)
Num C C 3 C P 4 C P 5 -- 6 C Parameter Run supply current measured at (CPU clock = 32 MHz, fBus = 16 MHz) Run supply current measured at (CPU clock = 51.34 MHz, fBus = 25.67 MHz) Run supply current measured at (CPU clock = 40 MHz, fBus = 20 MHz) Wait mode supply current measured at (CPU clock = 8 MHz, fBus = 4 MHz) (FEI mode, all modules off) Stop3 mode supply current C P C P6 7 P C P C P6 P Stop2 mode supply current C P C P6 8 P C P C P6 P C 9 RTC adder to stop2 or stop37 -40C 25C 85C 105C 125C -40C 25C 85C 105C 125C S23IDDRTC 5 3 3 S2IDD 5 0.94 1.25 7 30 64 0.83 1.1 6.3 25 57 300 300 -- -- 25 65 120 -- -- 20 55 100 500 500 nA nA A A -40C 25C 85C 105C 125C -40C 25C 85C 105C 125C 3 S3IDD 5 0.96 1.3 7.5 37 65 0.85 1.2 6.5 32.7 58 -- -- 25 90 150 -- -- 20 80 130 A A
5 4
Symbol
VDD (V) 5
Typ1 9.4 9 14.3 13.9 16 -- 2.7
Max2 10
Unit
RIDD
mA 3 5 10 30 mA 3 5 3 5 20 30 mA -- -- mA
RIDD
RIDD
WIDD
MC9S08MP16 Series Data Sheet, Rev. 1 16 Freescale Semiconductor
Electrical Characteristics
Table 8. Supply Current Characteristics (continued)
Num C C 10 C Adder to stop3 for oscillator (EREFSTEN =1) enabled8 Parameter LVD adder to stop3 (LVDE = LVDSE = 1) Symbol S3IDDLVD S3IDDOSC VDD (V) 5 3 11
1 2 3 4 5 6
Typ1 110 90 5
Max2 180 160 8
Unit A A A
5,3
7 8
Typical values are based on characterization data at 25C. See Figure 9 through Figure 14 for typical curves across temperature and voltage. Max values in this column apply for the full operating temperature range of the device unless otherwise noted. All modules except ADC active, ICS configured for FBELP, and does not include any dc loads on port pins All modules except ADC active, ICS configured for FEI, and does not include any dc loads on port pins All modules except ADC active, ICS configured for FEI, and does not include any dc loads on port pins Stop currents are tested in production for 25C on all parts. Tests at other temperatures depend upon the part number suffix and maturity of the product. Freescale may eliminate a test insertion at a particular temperature from the production test flow once sufficient data has been collected and is approved. Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. Values given under the following conditions: low range operation (RANGE = 0) with a 32.768kHz crystal and low power mode (HGO = 0).
16 FBE 14 12 FEI
Run Idd (mA)
10 8 6 4 2 0 2 8 16 20 25
fbus (MHz)
Figure 9. Typical Run IDD vs. Bus Frequency (VDD = 5V)
MC9S08MP16 Series Data Sheet, Rev. 1 Freescale Semiconductor 17
Electrical Characteristics
6 FBE 5 FEI
Run IDD (mA)
4
3
2
1 -40 0 25 85 105 125
Temperature (C) Figure 10. Typical Run IDD vs. Temperature (VDD = 5V, fbus = 8MHz)
16 FBE 14 12 FEI
Run Idd (mA)
10 8 6 4 2 0 2 8 16 20 25
fbus (MHz)
Figure 11. Typical Run IDD vs. Bus Frequency (VDD = 3V)
MC9S08MP16 Series Data Sheet, Rev. 1 18 Freescale Semiconductor
Electrical Characteristics
6 FBE 5 FEI
Run IDD (mA)
4 3
2
1 -40 0 25 85 105 125
Temperature (C)
Figure 12. Typical Run IDD vs. Temperature (VDD = 3V, fbus = 8MHz)
70 STOP2 60 50 STOP3
Stop IDD (uA)
40 30 20 10 0 -40 25 85 105 125
Temperature (C)
Figure 13. Typical Stop IDD vs. Temperature (VDD = 5V)
MC9S08MP16 Series Data Sheet, Rev. 1 Freescale Semiconductor 19
Electrical Characteristics
70 STOP2 60 50 STOP3
Stop IDD (uA)
40 30 20 10 0 -40 25 85 105 125
Temperature (C)
Figure 14. Typical Stop IDD vs. Temperature (VDD = 3V)
2.8
Num C
External Oscillator (XOSC) Characteristics
Table 9. Oscillator Electrical Specifications (Temperature Range = -40 to 105C Ambient)
Rating Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) flo FEE2 or FBE3 mode fhi fhi-hgo fhi-lp C1, C2 32 1 1 1 -- -- -- -- 38.4 16 16 8 kHz MHz MHz MHz Symbol Min Typ1 Max Unit
1
C
High range (RANGE = 1)
High range (RANGE = 1, HGO = 1) FBELP mode High range (RANGE = 1, HGO = 0) FBELP mode 2 -- Load capacitors Feedback resistor 3 -- Low range (32 kHz to 100 kHz) High range (1 MHz to 16 MHz) Series resistor Low range, low gain (RANGE = 0, HGO = 0) Low range, high gain (RANGE = 0, HGO = 1) High range, low gain (RANGE = 1, HGO = 0) 4 -- High range, high gain (RANGE = 1, HGO = 1) 8 MHz 4 MHz 1 MHz
See crystal or resonator manufacturer's recommendation.
RF
-- --
10 1
-- --
M
-- -- RS --
0 100 0
-- -- -- k
-- -- --
0 0 0
0 10 20
MC9S08MP16 Series Data Sheet, Rev. 1 20 Freescale Semiconductor
Electrical Characteristics
Table 9. Oscillator Electrical Specifications (Temperature Range = -40 to 105C Ambient) (continued)
Num C Crystal start-up time 4 Low range, low gain (RANGE = 0, HGO = 0) 5 T Low range, high gain (RANGE = 0, HGO = 1) High range, low gain (RANGE = 1, HGO = 0)5 High range, high gain (RANGE = 1, HGO = 1)4 Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE mode 2 6 T FBE mode 3 FBELP mode
1 2 t t CSTL-LP CSTL-HGO t CSTH-LP t CSTH-HGO
Rating
Symbol
Min
Typ1
Max
Unit
-- -- -- --
200 400 5 20
-- -- -- -- ms
fextal
0.03125 0 0
-- -- --
51.34 51.34 51.34
MHz MHz MHz
Typical data was characterized at 5.0 V, 25C or is recommended value. The input clock source must be divided using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3 The input clock source must be divided using RDIV to less than or equal to 39.0625 kHz. 4 This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve specifications. 5 4 MHz crystal
MCU EXTAL XTAL RS
RF
C1
Crystal or Resonator
C2
2.9
Num 1a C P
Internal Clock Source (ICS) Characteristics
Table 10. ICS Frequency Specifications (Temperature Range = -40 to 105C Ambient)
Characteristic Average internal reference frequency -- factory trimmed (consumer- and industrial-qualified devices) at VDD = 5 V and temperature = 25C Average internal reference frequency -- factory trimmed (automotive-qualified devices) at VDD = 5 V and temperature = 25C Internal reference frequency -- user trimmed Internal reference start-up time Symbol fint_t Min -- Typ1 32.768 Max -- Unit kHz
1b 2 3
P P T
fint_t fint_t tirefst
-- 31.25 --
31.25 -- 60
-- 39.06 100
kHz kHz s
MC9S08MP16 Series Data Sheet, Rev. 1 Freescale Semiconductor 21
Electrical Characteristics
Table 10. ICS Frequency Specifications (Temperature Range = -40 to 105C Ambient) (continued)
Num C P Characteristic Symbol Min 16 fdco_t 32 48 -- fdco_DMX32 -- -- fdco_res_t fdco_res_t fdco_t fdco_t tAcquire CJitter -- -- -- -- -- -- Typ1 -- -- -- 19.92 39.85 59.77 0.1 0.2 0.8 0.5 -- 0.02 Max 20 40 60 -- -- -- 0.2 0.4 2 1 1 0.2 %fdco %fdco %fdco %fdco ms %fdco MHz MHz Unit
4
Low range (DRS=00) DCO output frequency range -- C Mid range (DRS=01) trimmed 2 P High range (DRS=10) P DCO output frequency 2 Reference = 32768 Hz and DMX32 = 1 Low range (DRS=00) Mid range (DRS=01) High range (DRS=10)
5
P P
6 7 8 9 10 11
1 2
C C C C
Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM) Total deviation of trimmed DCO output frequency over voltage and temperature Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0C to 70 C
C FLL acquisition time 3 C Long term jitter of DCO output clock (averaged over 2-ms interval) 4
Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f Bus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval.
MC9S08MP16 Series Data Sheet, Rev. 1 22 Freescale Semiconductor
Electrical Characteristics
3% Deviation from Trimmed Frequency 2% 1% 0% -1% -2% -3% -40 -20 0 20 40 60 80 100 120 Temperature (C)
Figure 15. Typical Frequency Deviation vs Temperature (ICS Trimmed to 25 MHz bus@25C, 5V, FEI)1
2.10
ADC Characteristics
Table 11. 12-bit ADC Operating Conditions
Conditions Absolute Symbol VDDA VADIN CADIN RADIN 12 bit mode fADCK > 4MHz fADCK < 4MHz 10 bit mode fADCK > 4MHz fADCK < 4MHz 8 bit mode (all valid fADCK) RAS -- -- -- -- -- fADCK 0.4 0.4 -- -- -- -- -- -- -- 2 5 5 10 10 8.0 4.0 MHz Min 2.7 VREFL -- -- Typ1 -- -- 4.5 3 Max 5.5 VREFH 5.5 5 Unit V V pF k k External to MCU Comment
Characteristic Supply voltage Input Voltage Input Capacitance Input Resistance Analog Source Resistance
ADC Conversion Clock Freq.
1
High Speed (ADLPC=0) Low Power (ADLPC=1)
Typical values assume VDDAD = 5.0V, Temp = 25C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production.
1. Based on the average of several hundred units from a typical characterization lot. MC9S08MP16 Series Data Sheet, Rev. 1 Freescale Semiconductor 23
Electrical Characteristics
SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS VADIN VAS Pad leakage due to input protection
ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN
ADC SAR ENGINE
+ -
+ -
CAS
RADIN INPUT PIN
RADIN
INPUT PIN
RADIN CADIN
INPUT PIN
Figure 16. ADC Input Impedance Equivalency Diagram Table 12. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
C T Characteristic Supply Current ADLPC=1 ADLSMP=1 ADCO=1 Supply Current ADLPC=1 ADLSMP=0 ADCO=1 Supply Current ADLPC=0 ADLSMP=1 ADCO=1 Supply Current ADLPC=0 ADLSMP=0 ADCO=1 ADC Asynchronous High Speed (ADLPC=0) Clock Source Low Power (ADLPC=1) Conditions Symb IDDA Min -- Typ1 133 Max -- Unit A Comment
T
IDDA
--
218
--
A
T
IDDA
--
327
--
A
T
IDDA
--
0.582
--
mA
P
fADACK
2 1.25
3.3 2
5 3.3
MHz
tADACK = 1/fADACK
MC9S08MP16 Series Data Sheet, Rev. 1 24 Freescale Semiconductor
Electrical Characteristics
Table 12. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
C D Characteristic Conversion Time (Including sample time) Sample Time Conditions Short Sample (ADLSMP=0) Long Sample (ADLSMP=1) Short Sample (ADLSMP=0) Long Sample (ADLSMP=1) T Temp Sensor Slope Temp Sensor Voltage Total Unadjusted Error -40C to 25C 25C to 125C 25C 12 bit mode 10 bit mode 8 bit mode Differential Non-Linearity 12 bit mode 10 bit mode3 8 bit mode Integral Non-Linearity
3
Symb tADC
Min -- --
Typ1 20 40 3.5 23.5 3.266 3.638 1.396 3.0 1 0.5 1.75 0.5 0.3 1.5 0.5 0.3 1.5 0.5 0.5 1.0 0.5 0.5 -1 to 0 -- -- 1 0.2 0.1
Max -- -- -- -- -- -- -- 6.5 2.5 1.0 3.5 1.0 0.5 4.5 1.0 0.5 0.0/ -3.0 1.5 0.5 +1.75/ -1.25 1 0.5 -- 0.5 0.5 -- 2.5 1
Unit ADCK cycles ADCK cycles mV/C
Comment See ADC chapter in the Reference Manual for conversion time variances
D
tADS
-- --
m
-- --
T T P T T P T T P T T P T T T T D
VTEMP25 ETUE
-- -- -- --
mV LSB2 Includes quantization
DNL
-- -- --
LSB2
12 bit mode 10 bit mode 8 bit mode
INL
-- -- --
LSB2
Zero-Scale Error
12 bit mode 10 bit mode 8 bit mode
EZS
-- -- --
LSB2
VADIN = VSSAD
Full-Scale Error
12 bit mode 10 bit mode 8 bit mode
EFS
-- -- --
LSB2
VADIN = VDDAD
Quantization Error
12 bit mode 10 bit mode 8 bit mode
EQ
-- -- --
LSB2
D
Input Leakage Error 12 bit mode 10 bit mode 8 bit mode
EIL
-- -- --
LSB2
Pad leakage4 * RAS
Typical values assume VDDAD = 5.0V, Temp = 25C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (VREFH - VREFL)/2N 3 Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes 4 Based on input pad leakage current. Refer to pad electricals.
1
MC9S08MP16 Series Data Sheet, Rev. 1 Freescale Semiconductor 25
Electrical Characteristics
2.11
* * *
Digital to Analog (DAC) Characteristics
The accuracy at worst case: +/- 1.5% maximum The settling time must be less than 100 ns When changing the output voltage level, the voltage glitch cannot be completely eliminated Table 13. 5-bit DAC Characteristics
Num 2 3 5 6
C D D D D
Characteristic Supply current adder (enabled) DAC reference inputs DAC step size DAC voltage range
Symbol IDDAC Vin Vstep Vdacout
Min -- VSSA 0.75 x Vin/32 Vin/32
Typical -- -- Vin/32 --
Max 20 VDDA 1.25 x Vin/32 Vin
Unit A V V V
2.12
Num 1 2 3 4 5 6 7 8
1 2
High Speed Comparator (HSCMP) Characteristics
Table 14. High Speed Comparator Electrical Specifications
C D D -- P C T T D Characteristic1 Supply current, High Speed Mode (EN=1, PMODE=1) Supply current, Low Speed Mode (EN=1, PMODE=0) Analog input voltage Analog input offset voltage Analog Comparator hysteresis Propagation Delay, High Speed Mode (EN=1, PMODE=1) Propagation Delay, Low Speed Mode (EN=1, PMODE=0) Analog comparator initialization delay Symbol IDDAHS IDDALS VAIN VAIO VH tDHS2 tDLS2 tAINIT Min -- -- VSSA -- 3.0 -- -- -- Typical 200 10 -- 5 9 70 400 400 VDDA 40 20.0 120 600 -- Max Unit A A V mV mV ns ns ns
All timing assumes slew rate control disabled and high drive strength enabled. Delay from analog input to the CMPxOUT output pin. Measured with an input waveform that switches 30 mV above and below the reference.
2.13
Num 1 C T
Programmable Gain Amplifier (PGA) Characteristics
Table 15. Programmable Gain Amplifier Electrical Specifications
Parameter Symbol IDDON -- -- IDDAOFF VIL -- VSSA 450 250 1 VDDA/2 550 300 10 VDDA nA V Min Typical Max Unit uA
Supply current adder * normal mode (LP=0) * low power mode (LP=1) Supply current adder (stand-by) Absolute analog input level
2 3
T T
MC9S08MP16 Series Data Sheet, Rev. 1 26 Freescale Semiconductor
Electrical Characteristics
Table 15. Programmable Gain Amplifier Electrical Specifications (continued)
Num 4 C D Parameter Differential input voltage Symbol VDIFFMAX Min
V DDA - 1.4 -(----------------------------2 x Gain
Typical
Max
V DDA - 1.4 ----------------------------2 x Gain
Unit V
)
0
5
T
Linearity (@ voltage gain)1 * 1x * 2x * 4x * 8x * 16x * 32x Max gain error PGA clock * normal mode (LP=0) * low power mode (LP=1) PGA sampling frequency3
LV 1 - 1/2 LSB 2 - 1/2 LSB 4 - 1 LSB 8 - 1 LSB 16 - 4 LSB 32 - 4 LSB EG fPGA -- -- fSAMPL -- -- 1 2 4 8 16 32 1 82 4
1 ---------------------------------------------------------------------------------------------------12 + 18 x NUM_CLK_GS 5 43 ------------------------------------------------------------------ + ------------- + ----------- f f f
PGA ADC BUS
V/V 1 + 1/2 LSB 2 + 1/2 LSB 4 + 1 LSB 8 + 1 LSB 16 + 4 LSB 32 + 4 LSB 2 82 4 -- Samples per second % MHz
6 7a
T D
7b
D
8 9
1 2
D D
Input signal bandwidth Charge pump clock frequency
BW fcpclk
0 100
fSAMPL / 8 fPGA / 4
fSAMPL / 2 --
Hz Hz
LSB in 12-bit resolution 8 MHz is required for PGA achieving 1 s sampling time. 3 ADC in 12-bit mode, long sampling time, f ADC = fPGA
2.14
AC Characteristics
This section describes timing characteristics for each peripheral system.
2.14.1
Num 1 2 3 4 5 6 C D P D D D D
Control Timing
Table 16. Control Timing
Rating Bus frequency (tcyc = 1/fBus) Internal low power oscillator period External reset pulse Reset low drive BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 3 width2 -40 to 105 C -40 to 125 C Symbol fBus fBus tLPO textrst trstdrv tMSSU tMSH Min DC DC 700 100 34 x tcyc 500 100 Typ1 -- -- -- -- -- -- -- Max 25.67 20 1300 -- -- -- -- Unit MHz MHz s ns ns ns s
MC9S08MP16 Series Data Sheet, Rev. 1 Freescale Semiconductor 27
Electrical Characteristics
Table 16. Control Timing (continued)
Num 7 C D Rating Keyboard interrupt pulse width Asynchronous path4 Synchronous path5 Port rise and fall time -- Low output drive (PTxDS = 0) (load = 50 pF)6 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) Port rise and fall time -- High output drive (PTxDS = 1) (load = 50 pF)6 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1)
1 2 3 4 5 6
Symbol tILIH, tIHIL tRise, tFall
Min 100 1.5 x tcyc
Typ1 -- --
Max -- --
Unit ns
8
C
ns -- -- 40 75 -- -- ns -- -- 11 35 -- --
tRise, tFall
Typical values are based on characterization data at VDD = 5.0V, 25C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD rises above VLVD. This is the minimum pulse width that is guaranteed to be recognized as a keyboard interrupt request in stop mode. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40C to 125C.
textrst RESET PIN
Figure 17. Reset Timing
tIHIL KBIxPn
KBIxPn tILIH
Figure 18. KBIxPn Timing
2.14.2
FTM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the FTM timer counter. These synchronizers operate from the current ICSOUT clock. The ICSOUT clock period = 0.5 x tcyc = 1/(fBus x 2). Table 17. FTM Input Timing
No. 1 2 3 C D D D Function External clock frequency External clock period External clock high time Symbol fTCLK tTCLK tclkh Min 0 2 0.75 Max fICSOUT/41 -- -- Unit Hz tcyc tcyc
MC9S08MP16 Series Data Sheet, Rev. 1 28 Freescale Semiconductor
Electrical Characteristics
Table 17. FTM Input Timing (continued)
No. 4 5
1
C D D
Function External clock low time Input capture pulse width
Symbol tclkl tICPW
Min 0.75 0.75
Max -- --
Unit tcyc tcyc
The maximum external clock frequency is limited to 10MHz due to input filter characteristics.
tTCLK tclkh
TCLK tclkl
Figure 19. FTM External Clock
tICPW FTMxCHn
FTMxCHn tICPW
Figure 20. FTM Input Capture Pulse
2.14.3
MTIM Module Timing
Synchronizer circuits determine the fastest clock that can be used as the optional external clock source to the MTIM timer counter. These synchronizers operate from the current bus rate clock. Table 18. MTIM Input Timing
No. 1 2 3 4 C D D D D Function External clock frequency External clock period External clock high time External clock low time Symbol fTCLK tTCLK tclkh tclkl
tTCLK tclkh
Min 0 4 1.5 1.5
Max fBus/4 -- -- --
Unit Hz tcyc tcyc tcyc
TCLK tclkl
Figure 21. MTIM Timer External Clock
MC9S08MP16 Series Data Sheet, Rev. 1 Freescale Semiconductor 29
Electrical Characteristics
2.14.4
SPI
Table 19. SPI Electrical Characteristics
Num1 1 C Cycle time D Enable lead time 2 D Enable lag time 3 D Clock (SPSCK) high time Master and Slave Clock (SPSCK) low time Master and Slave Data setup time (inputs) 6 D Data hold time (inputs) 7 8 9 10 D D D D Data hold time (outputs) 11 D Operating frequency 12 D Master Slave Master Slave (SPIFE=0) (SPIFE=0) (SPIFE=1) (SPIFE=1) Master Slave Access time, slave3 Disable time, slave4 Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave tSCK tSCK 2 4 -- 1/2 4096 Rating2 Symbol Min Max Unit tcyc tcyc
Table 19 and Figure 22 through Figure 25 describe the timing requirements for the SPI system.
--
1/2 --
tLead tLead tLag tLag tSCKH tSCKL tSI(M) tSI(S) tHI(M) tHI(S) tA tdis tSO tSO tHO tHO fop
tSCK tSCK tSCK tSCK
ns ns ns ns
-- 1/2
1/2 -- -- -- -- --
4 5
D D
1/2 tSCK - 25 1/2 tSCK - 25 30 30
30 30 0 -- -- --
-- -- 40 40 25 25
ns ns ns ns ns ns
Data setup time (outputs)
-10 -10
-- --
ns ns
fBus/4096 dc fBus/4096 dc
85 fBus/4 56 56
MHz MHz MHz
1 2 3 4 5 6
Refer to Figure 22 through Figure 25. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. Time to data active from high-impedance state. Hold time to high-impedance state. Maximum baud rate must be limited to 8 MHz. Maximum baud rate must be limited to 5 MHz due to input filter characteristics.
MC9S08MP16 Series Data Sheet, Rev. 1 30 Freescale Semiconductor
Electrical Characteristics
SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 6 MISO (INPUT) MSB IN2 10 MOSI (OUTPUT) MSB OUT2 7 BIT 6 . . . 1 10 BIT 6 . . . 1 LSB OUT LSB IN 11 1 5 4 3
5 4
NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 22. SPI Master Timing (CPHA = 0)
SS(1) (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) MISO (INPUT) 10 MOSI (OUTPUT) MSB OUT(2) 5 4 5 4 6 7 MSB IN(2) BIT 6 . . . 1 11 BIT 6 . . . 1 LSB OUT LSB IN 3
NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 23. SPI Master Timing (CPHA = 1)
MC9S08MP16 Series Data Sheet, Rev. 1 Freescale Semiconductor 31
Electrical Characteristics
SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO (OUTPUT) SLAVE 6 MOSI (INPUT)
NOTE:
3 5
4
5 4 10 MSB OUT 7 MSB IN BIT 6 . . . 1 LSB IN BIT 6 . . . 1 11 SLAVE LSB OUT SEE NOTE 9
1. Not defined but normally MSB of character just received
Figure 24. SPI Slave Timing (CPHA = 0)
SS (INPUT) 1 2 SCK (CPOL = 0) (INPUT) SCK (CPOL = 1) (INPUT) MISO (OUTPUT) SEE NOTE 8 MOSI (INPUT) 5 4 5 4 10 SLAVE 6 MSB IN MSB OUT 7 BIT 6 . . . 1 LSB IN 11 BIT 6 . . . 1 SLAVE LSB OUT 9 3
NOTE: 1. Not defined but normally LSB of character just received
Figure 25. SPI Slave Timing (CPHA = 1)
MC9S08MP16 Series Data Sheet, Rev. 1 32 Freescale Semiconductor
Electrical Characteristics
2.15
Flash Memory Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section. Table 20. Flash Memory Characteristics
Num 1 2 3 4 5 6 7 8 9 10 11 12
1 2
C -- -- -- -- C -- D D C C C C
Characteristic Supply voltage for program/erase -40C to 125C Supply voltage for read operation Internal FCLK frequency1
Symbol Vprog/erase VRead fFCLK tFcyc tprog tBurst tPage tMass RIDDBP RIDDPE
Min 2.7 2.7 150 5
Typical
Max 5.5 5.5 200 6.67
Unit V V kHz s tFcyc tFcyc tFcyc tFcyc
Internal FCLK period (1/FCLK) Byte program time (random location)2 Byte program time (burst Page erase Mass erase time2 time2 mode)2
9 4 4000 20,000 -- -- 10,000 4 6 -- 100,000 100 -- -- -- -- --
Byte program current3 Page erase current
3
mA mA cycles years
Program/erase TL to TH = -40C to + 125C T = 25C Data retention5 tD_ret
endurance4
15
The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures with VDD = 5.0 V, bus frequency = 4.0 MHz. 4 Typical endurance for Flash is based upon the intrinsic bit cell performance. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
2.16
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
2.16.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
MC9S08MP16 Series Data Sheet, Rev. 1 Freescale Semiconductor 33
Ordering Information
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported emissions levels. Table 21. Radiated Emissions, Electric Field
Parameter Symbol Conditions Frequency 0.15 - 50 MHz 50 - 150 MHz Radiated emissions, electric field VRE_TEM VDD = 5V TA = +25C package type 48 LQFP 150 - 500 MHz 500 - 1000 MHz IEC Level
2
fOSC/fBUS
Level1 (Max) 3 8
Unit
dBV
4 MHz crystal 2 MHz bus
-4 -8 N 1 -- --
SAE Level3
1
Data based on qualification test results. The reported emission level is the value of the maximum emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2 IEC level maximums: N 12 dBV, L 24 dBV, I 36 dBV 3 SAE level maximums: 1 10 dBV, 2 20 dBV, 3 30 dBV, 4 40 dBV
3
Ordering Information
Table 22. Device and Package Options
Available Packages2 RAM 48-Pin 32-Pin 28-Pin
This section contains ordering information for MC9S08MP16 and MC9S08MP12 devices.
Device Number1
Temp Range
Memory Flash
Consumer and Industrial Qualification MC9S08MP16 MC9S08MP12 V V 16K 12K 1024 512 48 LQFP -- 32 LQFP -- 28 SOIC 28 SOIC
Automotive Qualification S9S08MP16
1
C, V, M
16K
1024
48 LQFP
--
--
See the MC9S08MP16RM Reference Manual (MC9S08MP16RM) for a complete description of modules included on each device. 2 See Table 23 for package information.
MC9S08MP16 Series Data Sheet, Rev. 1 34 Freescale Semiconductor
Package Information
3.1
Device Numbering Scheme
xx 9 S08 MP nn E2 y zz Status MC = Consumer & Industrial S = Automotive Qualified Memory 9 = Flash-based Core Family Package designator (see Table 23) Temperature range V = -40C to 105C M = -40C to 125C Wafer fab site and mask revision
(this field appears only in automotive-qualified part numbers)
Example of the device numbering system:
Flash size 16 KBytes 12 KBytes
4
Package Information
The latest package outline drawings are available on the product summary pages on our web site: http://www.freescale.com/8bit. The following table lists the document numbers per package. Use these numbers in the web page's keyword search engine to find the latest package outline drawings.
NOTE
The 32 LQFP and 28 SOIC are not qualified to meet automotive requirements. Table 23. Package Descriptions
Pin Count 48 32 28 Package Type Low Quad Flat Pack Low Quad Flat Pack Small Outline Integrated Circuit Abbreviation LQFP LQFP SOIC Designator LF LC WL Case No. 932-03 873A-03 751F-05 Document No. 98ASH00962A 98ASH70029A 98ASB42345B
5
Related Documentation
Reference Manual (MC9S08MP16RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information.
Find the most current versions of all documents at http://www.freescale.com.
6
Revision History
http://www.freescale.com
To provide the most up-to-date information, the revision of our documents on the World Wide Web are the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
MC9S08MP16 Series Data Sheet, Rev. 1 Freescale Semiconductor 35
Table 24 summarizes changes contained in this document. Table 24. Revision History
Rev 1 Date 10/6/2009 Initial public revision Description of Changes
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Document Number: MC9S08MP16
Rev. 1 10/2009

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